The disclosed invention is directed generally to circuitry for speed testing memory devices, and more particularly to circuitry for efficiently speed testing a memory device by writing complementary data into complementary memory address locations, and performing a read of a predetermined address immediately followed by a read of the 1's complement of the predetermined address.
A known speed testing technique performs a speed test for each address transition that includes a change of at least one address bit. In other words, data is read from one address and then from another address for every address change possible. Considerations with speed testing that tests every possible address transition is tester time and expense, since the number of memory accesses is significant. For an N-bit wide address, at least 2.sup.2N -2.sup.N memory accesses are required. An 8-bit address would therefore require at least 65,280 memory accesses. A 16-bit address would require at least 4,294,901,760 memory accesses.